Intel has processed more than one million 300-millimeter silicon wafers using High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography, marking a major production milestone announced Monday at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference in Monterey, California. The achievement underscores Intel’s early lead in adopting next-generation chipmaking technology as the semiconductor industry races to sustain Moore’s Law.
The one million wafers span multiple stages: early tool certification and testing, research and development efforts, and volume production on select layers for a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake, manufactured on Intel’s 18A process node. According to Intel Foundry and ASML, overlay, throughput, and availability metrics are meeting Intel Foundry’s expectations, and products manufactured on Intel 18A using High-NA for select layers are delivering performance that meets or exceeds comparable layers patterned using conventional EUV technology.
High-NA EUV represents a significant leap forward in lithography technology. The systems operate at a numerical aperture of 0.55, compared to 0.33 for conventional EUV, enabling much finer patterning and denser chip designs. This improvement facilitates a 2.8-fold boost in feature density and allows chipmakers to return to single-patterning techniques for certain layers, reducing complexity and production time.
Intel installed its first commercial High-NA EUV lithography system, ASML’s TWINSCAN EXE:5200B, in 2024 and became the first manufacturer to ship high-volume logic products using the technology in July 2026. The company qualified High-NA EUV for select layers of its Intel 18A process and is now planning broader deployment on its forthcoming Intel 14A node, expected to enter risk production in late 2026 or early 2027.
Competitive Positioning and Industry Adoption
Intel’s aggressive High-NA deployment contrasts sharply with competitors’ more cautious approaches. TSMC, historically the leader in advanced lithography adoption, has delayed High-NA EUV deployment until 2029 or later, citing cost concerns and the substantial investment required for the $350 million machines. Samsung Electronics is taking a similarly measured approach, planning to delay commercial deployment of High-NA EUV until its 1-nanometer process node around 2030.
This divergence reflects a strategic bet by Intel that early adoption of High-NA technology will provide a durable advantage in performance and manufacturing efficiency. Naga Chandrasekaran, Intel Executive Vice President and Co-General Manager of Intel Foundry, stated that companies building complex AI products need manufacturing innovations that are production-ready and easy to use. Intel is focused on near-term enablement of High-NA on current 6-inch mask formats with or without stitching techniques, while also working toward larger 6-by-12-inch mask formats that will unlock further scaling.
The milestone reflects years of collaboration between Intel and ASML, the Dutch semiconductor equipment manufacturer. ASML President and CEO Christophe Fouquet recognized Intel Foundry’s pioneering role, noting the company’s progression from installing the first commercial EXE system in 2024 to qualifying the latest-generation tools and shipping the first high-volume logic product manufactured with High-NA EUV technology.
Sources
- Business Wire / Yahoo Finance — Intel Foundry and ASML press release announcing one million wafers processed, performance metrics, and strategic focus on 6-inch and 6×12-inch mask formats
- StreetInsider — Summary of Intel and ASML announcement with overlay, throughput, and performance details; quotes from Fouquet and Chandrasekaran
- ASML Press Release (July 15, 2026) — Initial announcement of High-NA EUV reaching production readiness with Intel 18A and Panther Lake qualification
- Tom’s Hardware — Confirmation of Intel 18A High-NA EUV deployment and first high-volume logic product shipment
- Semiwiki — Intel and TSMC divergent High-NA EUV strategies; TSMC’s delayed adoption timeline
- Persistence Market Research — Feature density improvements (2.8x boost) from High-NA EUV advancement from 0.33 NA to 0.55 NA
